1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a Schmitt trigger inverter circuit, made with only four transistors, and a corresponding fabrication process.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a CMOS inverter, and diagrams of an ideal output waveform and input-output transfer characteristics (prior art). Problems can arise when digital signals are interfaced with circuitry, especially if the digital input signals are corrupted by noise. The input stages of most digital circuits are designed adhering to pre-specified input amplitude levels for logic 0 (low) and logic 1 (high). For complementary metal-oxide-semiconductor (CMOS) implementations, these levels, designated VIL and VIH, are set to 1.3V and 3.7V, respectively, using a 5V supply voltage referenced to ground. For transistor-to-transistor logic (TTL), VIL and VIH are at 0.8V and 2.0V, respectively, using a 5V supply voltage referenced to ground. Input signals below VIL are interpreted as logic 0, and signals above VIH as logic 1. Because of these levels, there exists a single input voltage level, designated as the “switching point” voltage VSP (also referred to in the literature as threshold voltage, but not to be confused with the threshold voltage of MOSFET transistors), which triggers a change in the output state of the digital circuit. With a 5V-supply, the CMOS VSP=2.5V, while for TTL VSP=1.5V. Ideally, VSP=VDD/2 for CMOS.
FIG. 2 is a diagram depicting the response of the CMOS inverter of FIG. 1 with a noise-corrupted input signal. Vout switches states erroneously due to noise-induced Vin excursion around VSP. Variations of the input level around VSP due to noise, which are not present when using an ideal input signal, cause interfacing digital circuitry, such as an input buffer, to change output states multiple times before stabilizing in the correct state. This undesirable situation propagates noise artifacts through the interface.
FIG. 3 is a schematic diagram of a conventional Schmitt trigger inverter circuit (prior art). One remedy for the noise problem depicted in FIG. 2 is to use digital circuits exhibiting an intentional amount of hysteresis in their DC transfer characteristics, such as the Schmitt trigger.
FIG. 4 depicts the response of a hysteresis CMOS inverter, with the noisy input signal of FIG. 2, and hysteresis DC transfer characteristics (prior art). The output switches states only when Vin>VSPH or Vin<VSPL. Thus, a higher-than-midpoint voltage input is required to generate a logic low output signal, while a lower-than-midpoint voltage input is need to generate a logic high output signal.
It would be advantageous if the size of a Schmitt trigger inverter circuit could be reduced by using transistors with greater functionality.
It would be advantageous if a Schmitt trigger inverter circuit could be made with transistors having built-in control functionality, to reduce the total number of transistors needed to build the circuit.